Tuesday, April 3, 2012

Twist/Change in project

Due to limitations as a result of  resources, materials and time-constraint. Moreover it is much more complicated sampling non-periodic signals.

I have added a little twist to the project. I have decided to work on something I am more familiar with and work with the knowledge I have been able to acquire so far through classes.

I created a clapper circuit some semesters ago but now I have decided to implement the same circuit using an FPGA.

STEPS
1. Create a design model of a clapper ciruit on simulink

Tuesday, February 21, 2012

Status Report - Tue 2.21.2012

NEXT GOAL
  • Learn how to quantize sampled voice signals using MATLAB


ACCOMPLISHMENTS
  • I was able to get helpful Handout from Dr Walker
  • I was able to Download and install Altera DSP Builder

 To do by Friday 2.24.2012:
  • Play around and get familiar with Altera's DSP Builder
  • Learn how to find Altera I/O & Bus on SIMULINK
  • Learn to use the Input Block within Altera I/O & Bus on SIMULINK

Sunday, February 19, 2012

Status Report - Fri 2.17.2012

ACCOMPLISHMENTS
  • Generated voice input using microphone on computer
  • Used wavread function on MATLAB to obtain store the .wav file in a variable
  • Plotted the voice signal to observe behavior using MATLAB
  • Sampled voice signal using a sampling frequency of 48kHz, knowing nyquist frequency to be about 20kHz.
  • Wrote a C code that simulates quantization of a discrete signal, represented as set of data in an array.

NEXT GOAL
  • Learn how to quantize sampled voice signals using MATLAB
  • Generate a digital filter using SIMULINK
 To do by Tuesday 2.21.2012:
  1. Find more material to boost knowledge on quantizing sampled signals using MATLAB.
  2. Meet advisor for helpful information and resources with regards to quantizing a sampled signal.

Monday, February 6, 2012

Step 1: Sampling My Voice using MATLAB

[y, fs] = wavread('C:\Users\Habad\Dropbox\SPRING 2012 CLASSES\EEGR491\myvoice.wav');
%w = [min(fs) max(fs)]
%sound(y,fs);
%plot(y);
%stem(y);
t=0:1/fs:(length(y)-1)/fs; %get sampling frequency
figure(1);
plot(t,y); %graph it – try zooming while its up…not much visible until you do

FIG 1: AUDIO SIGNAL PLOT WITHOUT NOISE


%clear
[y,fs] = wavread('C:\Users\Habad\Dropbox\SPRING 2012 CLASSES\EEGR491\myvoice_nonoise.wav');
%w = [min(fs) max(fs)]
%sound(y,fs);
%plot(y);
%stem(y);
t=0:1/fs:(length(y)-1)/fs; %get sampling frequency
figure(2);
plot(t,y); %graph it – try zooming while its up…not much visible until you do



FIG 2: AUDIO SIGNAL PLOT WITH NOISE


COMMENTS
So far, I have been able to input my voice as a .wav audio signal. I then sampled it. For the quantization which is step 2, I started writing a function but I decided to write a C code with similar algorithm that would perform the same operation. The program would take in a string of discrete values and then assigned each one of the discrete values to a level. This was taken as a step to enable me understand exactly how the quantization would take place.
C CODE (Incomplete)
int main()
{
    int quant[8] = {0,1,2,3}; //levels
   
    int y, yq, i;
   
    y = [2,3,4,5,6,8,1,2,4,5,2,4,5,6,0,3,4,-1,4,5,1,2,10,9]; //input signal
   
    for (i = 0; i <0; i++)
    {
        //B = 4, number of levels
        //so break max and min into 4 different levels/ranges
        //how many numbers are between max and min, then divide that number by number of levels i.e. 4
        //min=-1, max = 10, so number of numbers  = 12, so there would be 4 elements per range
       
       
         yq = quant[i]; //quantized
    }
   
    system("pause");
    return 0;
}

Monday, November 14, 2011

COUNTER USING AN FPGA

I have decided to implement a counter as a start for FPGA applications.

I wrote the following verilog code of a counter from 0 to 8 for my digital electronics class & thought it would be a great idea to implement it on an FPGA Board;



module counter (count, clk, reset);
output [8:0] count;
input clk, reset;

reg [8:0] count;
parameter tpd_reset_to_count = 3;
parameter tpd_clk_to_count   = 2;

function [8:0] increment;
input [8:0] val;
reg [3:0] i;
reg carry;
  begin
    increment = val;
    carry = 1'b1;
    /*
     * Exit this loop when carry == zero, OR all bits processed
     */
    for (i = 4'b0; ((carry == 4'b1) && (i <= 8));  i = i+ 4'b1)
       begin
         increment[i] = val[i] ^ carry;
         carry = val[i] & carry;
       end
  end      
endfunction

always @ (posedge clk or posedge reset)
  if (reset)
     count = #tpd_reset_to_count 8'h00;
  else
     count <= #tpd_clk_to_count increment(count);

endmodule

Tuesday, November 1, 2011

Easily Installed Project on DE2

There are a couple of easily accessible projects installed for the DE2. I have made a temporary decision to change the focus of my FPGA research project as advised by my advisor, Dr Walker. I would update this blog on Friday with information about this new project I would be choosing to complete as the semester comes to an end.