RESEARCH UPDATE - Week of 10/24

The past few weeks have been really challenging due to my work load, alongside responsibilities. I haven't been updating this blog as often as I used to for this reason.

I temporarily suspended the speech recognition project for a while due to on going research into my background understanding and revaluation of requirements and goals to achieve. I met with Dr Walker some weeks back and he asked me what options are there for me to upload my program into the FPGA and/or development board. There were multiple answers to this question. One option was to use simulink and another option was to use Model Sim alongside Quartus II. This provides a platform to both simulate and run my program on the FPGA board.

As I said earlier, I got in touch with a couple of valuable contacts. Carlos has been very resourceful with information. Honestly, as we all know, the speech recognition project is a very tasking project and would require a high level of competence within the field. I am glad this project has made me see the good, bad and ugly sides of how a research project could go. I love the fact that these create challenges and my top goal for this research project is to never give up. The more challenging a task, the more research and work I put into it and thus, the more I learn and experience I derive.

I had been working the arduino microcontrollers all semester and now the second half of my microprocessors class involves xilinx FPGAs. Although Xilinx and Altera have differences, they operate the same way. I am taking all my electives this semester and most of my classes this semester are directly or indirectly related the speech recognition project. Everyday, I often learn more and develop a deeper understanding of what I'm getting into, The question now is what is my current status? The truth is that there are no single answers to the questions. At the moment, I am learning more and gaining insight into how to get the work done. As I look forward to working with Xilinx in my class, I hope I would learn as much so as to enable my project move forward. My Digital Signal processing class is also a very valuable asset for my project. I spoke to my DSP professor, Dr Clarke, about my idea and project some weeks back and he really loved it. Although, he agreed to the fact that the project would involve a lot of computations, I still till today believe I can bring my speech recognition device to life. I never give up until I achieve my goal.

Furthemore, I am pleased to announce that I participated in the IEEE Xtreme 5.0 programming competition from Friday to Saturday 10.24.2011. This was a honored privilege as I was a part of the pioneer programmers from Morgan State University who participated in the competition.

DESIGN APPROACH

I haven't been chanced to update my blog in a couple of weeks but that didn't mean I couldnt't get work done. During the long break, I was able to contact a member of the team from McGrill University; Carlos Asmat, who had previously worked on a speech recognition device successfully. This project has involved me networking with alot of people including professors both with and outside Morgan State University.

I met with Dr Walker last week and we spoke about simulation and testing. We discussed about software preferences and the options to pick between ModelSim and Simulink. I have had issues working around ModelSim alongside Quartus II but since Simulink has a DSP builder module for altera, I would be giving simulink a try.


This does not mean I won't go back to Quartus II as it is my prefered CAD software. 
The semester is getting busy everyday and as a result, my progress has become a bit slow but I haven't let that affect my work.

Creating a speech recognition device using FPGA technology

PROJECT: Speech Recognition Device Using FPGA Technology

I have decided on developing a device which would have a speech interface. I will be using my knowledge on FPGAs so far and my knowledge in digital signal processing to develop this real-time speech recognition device that would interact with the surrounding using analog (audio) inputs from a user. I would still be using Verilog Hardware Description Language to implement my design with the aid of block diagrams showing dataflow and control flow.

EQUIPMENTS

Development Kit: Altera DE2 – Cyclone II FPGA

Software: ModelSim-Altera Edition, Quartus II, MATLAB and maybe NIOS II.

The project would include the following implementations

·         Design approach

·         A/D Conversion

·         Word detector

·         FFT

·         Memory Management

·         Distance Computation

For the design, I would be using Quartus II to create Verilog blocks as well as CAD. I would also need datapath and intermediate controllers. The Development kit contains the Cyclone II FPGA, CODEC and Analog-to-digital converter integrated. I would be using three memory modules which include FLASH, SDRAM and SRAM. With the help of Quartus II, I would design a 1024-points FFT module and a distance computation module using Verilog.

I have learned to work with Quartus II over the past weeks and would currently proceed in understanding the background theories behind the design, Analog-to-digital converter, FFT and distance computation modules, and memory management. I would spend the next 2 weeks researching into these areas to help develop a better understanding for my hardware implementation