I wrote the following verilog code of a counter from 0 to 8 for my digital electronics class & thought it would be a great idea to implement it on an FPGA Board;
module counter (count, clk, reset);
output [8:0] count;
input clk, reset;
reg [8:0] count;
parameter tpd_reset_to_count = 3;
parameter tpd_clk_to_count = 2;
function [8:0] increment;
input [8:0] val;
reg [3:0] i;
reg carry;
begin
increment = val;
carry = 1'b1;
/*
* Exit this loop when carry == zero, OR all bits processed
*/
for (i = 4'b0; ((carry == 4'b1) && (i <= 8)); i = i+ 4'b1)
begin
increment[i] = val[i] ^ carry;
carry = val[i] & carry;
end
end
endfunction
always @ (posedge clk or posedge reset)
if (reset)
count = #tpd_reset_to_count 8'h00;
else
count <= #tpd_clk_to_count increment(count);
endmodule
