Update 9/13/2011: Verilog HDL & Algorithm

I have decided that the HDL I am going to use is Verilog. As a step forward in my project, I have decided to revise and refresh my knowledge on verilog coding. I went over various tutorials and techniques. I am yet to go over materials for the Altera FPGA but I am pretty much developing an algorithm for my design as of right now.

I'd like to divide my project into 5 different parts;

1. Specification: This is the point at which I would define the parameters in my design that I plan to use.

2. High Level Design: This is the point where I define various blocks/modules within my design and how they communicate with each other

3. Low Level Design: This is the point where I define how each block is implemented

4. RTL Coding: This is the point where I convert my low level design into verilog code

5. Simulation: This is the point where I verify the functionality of the model of program I wrote in verilog